1. Field of the Invention
This invention relates to digital memories and more particularly to methods and apparatus for reading data from a digital memory.
2. Description of the Related Art
FIG. 1 is a circuit diagram of a prior art digital memory sensing architecture. As shown, a memory 10 comprises a plurality of memory cells 12 in a row by column format. Each of a plurality of read bitlines 14 (where there is one read bitline per column) is coupled to a column multiplexer 16 which selects a desired bitline and provides it to a sense amplifier 18, which senses the value of the bitline (1 or 0) and provides the corresponding output. In a memory implemented with MOS technology, before a read is initiated, the bitlines 14 are precharged to a supply voltage less the threshold voltage V.sub.tn of a MOS transistor. Also, the input to the sense amplifier 18 is precharged to the supply voltage.
Each of the bit lines 14 such as bit line 14a has an associated n-type precharge transistor 20, that receives a precharge signal. The precharge signal turns on the precharge transistor 20, thus bringing the bit line 14a to the supply voltage (V.sub.dd) less the transistor threshold voltage (V.sub.tn).
A sense amplifier precharge circuit comprises a p-channel transistor 24 whose gate is coupled to the output of an invertor 21. The sense amplifier precharge circuit serves to precharge the sense amplifier input node to V.sub.dd. In particular, the invertor 21 receives the precharge signal at its input and thus provides a low output when the precharge signal goes high. Thus, when the output of the invertor 21 goes low, the p-channel 24 pulls up the sense amplifier input node to V.sub.dd.
It would be desirable to have a sensing architecture that has faster read access but less power consumption than the circuit shown in FIG. 1.